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19-3024; Rev 0; 10/03
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
General Description
The MAX5942A/MAX5942B integrate a complete power IC for powered devices (PD) in a power-over-ethernet (PoE) system. The MAX5942A/MAX5942B provide a PD interface and a compact DC-DC PWM controller suitable for flyback and forward converters in either isolated or nonisolated designs. The MAX5942A/MAX5942B PD interface complies with the IEEE 802.3af standard, providing the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. These devices also feature power-mode undervoltage lockout (UVLO) with wide hysteresis and powergood status outputs. The MAX5942A/MAX5942B also integrate all the building blocks necessary for implementing DC-DC fixedfrequency isolated power supplies. This device is a current-mode controller with an integrated high startup circuit suitable for isolated telecom/industrial voltage range power supplies. A high-voltage startup circuit allows the PWM controller to draw power directly from the 18V to 67V input supply during startup. The switching frequency is internally trimmed to 275kHz 10%, thus reducing magnetics and filter components. The MAX59412A allows an 85% operating duty cycle and can be used to implement flyback converters. The MAX5942B limits the operating duty cycle to less than 50% and can be used in single-ended forward converters. The MAX5942A/MAX5942B are designed to work with or without an external diode bridge in front of the PD. The MAX5942A/MAX5942B are available in 16-pin SO packages.
Features
o Powered Device Interface Fully Integrated IEEE 802.3af-Compliant PD Interface PD Detection and Programmable Classification Signatures Less than 10A Leakage Current Offset During Detection Integrated MOSFET for Isolation and Inrush Current Limiting Gate Output Allows External Control of the Internal Isolation FET Programmable Inrush Current Control/ULVO PGOOD/PGOOD Outputs Enable PWM Controller o PWM Controller Wide Input Range: 18V to 67V Isolated (Without Optocoupler) or Nonisolated Power Supply Current-Mode Control Leading-Edge Blanking Internally Trimmed 275kHz 10% Oscillator Soft-Start
MAX5942A/MAX5942B
Ordering Information
PART MAX5942AESE* MAX5942ACSE MAX5942BESE* MAX5942BCSE TEMP RANGE -40C to +85C 0C to +70C -40C to +85C 0C to +70C PINPACKAGE 16 SO 16 SO 16 SO 16 SO MAX DUTY CYCLE (%) 85 85 50 50
Applications
IP Phones Wireless Access Nodes Internet Appliances Computer Telephony Security Cameras Power Devices in Power-Over-Ethernet/ Power-Over-MDI
*Future product--contact factory for availability.
Pin Configuration
TOP VIEW
V+ 1 VDD 2 FB 3 SS_SHDN 4 ULVO 5 16 VCC 15 NDRV 14 V-
MAX5942A MAX5942B
13 CS 12 GND 11 PGOOD 10 PGOOD 9 OUT
Typical Operating Circuit appears at end of data sheet.
RCL 6 GATE 7 VEE 8
SO
________________________________________________________________ Maxim Integrated Products
1
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
ABSOLUTE MAXIMUM RATINGS
(All voltages are referenced to VEE, unless otherwise noted.) GND........................................................................-0.3V to +80V OUT, PGOOD ...........................................-0.3V to (GND + 0.3V) RCL, GATE .............................................................-0.3V to +12V UVLO ........................................................................-0.3V to +8V PGOOD to OUT.........................................-0.3V to (GND + 0.3V) V+ to V-...................................................................-0.3V to +80V VDD to V-.................................................................-0.3V to +40V VCC to V-..............................................................-0.3V to +12.5V FB, NDRV, SS_SHDN, CS to V- ..................-0.3V to (VCC + 0.3V) Maximum Input/Output Current (continuous) OUT to VEE ...................................................................500mA GND, RCL to VEE ............................................................70mA UVLO, PGOOD, PGOOD to VEE .....................................20mA GATE to VEE ....................................................................80mA VDD, VCC .........................................................................20mA NDRV Continuous ...........................................................25mA NDRV (pulsed for less than 1s) .......................................1A Continuous Power Dissipation (TA = +70C) 16-Pin SO (derate 9.1mW/C above +70C)................727mW Operating Temperature Ranges MAX5942_CSE...................................................0C to +70C MAX5942_ESE ................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied to OUT, V+ tied to GND, UVLO = VEE, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER PD INTERFACE DETECTION MODE Input Offset Current Effective Differential Input Resistance CLASSIFICATION MODE Classification Current Turn-Off Threshold VTH,CLSS VIN rising (Note 4) Class 0, RCL = 10k VIN = 12.6V Class 1, RCL = 732 to 20V, RDISC Class 2, RCL = 392 = 25.5k Class 3, RCL = 255 (Notes 5, 6) Class 4, RCL = 178 VIN = (GND - VEE) Measure at GND, not including RDISC VIN increasing, UVLO = VEE 37.4 30 7.4 Set UVLO externally (Note 7) VUVLO increasing Ratio to VREF,UVLO 12 2.400 19.2 2.460 20 67 2.522 20.9 0.4 38.6 20.8 0 9.17 17.29 26.45 36.6 21.8 22.5 2 11.83 19.71 29.55 41.4 67 1 40.1 V mA V V V V V % mA V IOFFSET dR VIN = 1.4V to 10.1V (Note 2) VIN = 1.4V up to 10.1V with 1V step, OUT = PGOOD = GND (Note 3) 550 10 A k SYMBOL CONDITIONS MIN TYP MAX UNITS
Classification Current
ICLASS
POWER MODE Operating Supply Voltage Operating Supply Current Default Power Turn-On Voltage Default Power Turn-Off Voltage Default Power Turn-On/Off Hysteresis External UVLO Programming Range UVLO External Reference Voltage UVLO External Reference Voltage Hysteresis VIN IIN VUVLO,ON
VUVLO,OFF VIN decreasing, UVLO = VEE VHYST,UVLO VIN,EX VREF,UVLO HYST
2
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied to OUT, V+ tied to GND, UVLO = VEE, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER UVLO Bias Current UVLO Input Ground Sense Threshold UVLO Input Ground Sense Glitch Rejection Power Turn-Off Voltage, Undervoltage Lockout Deglitch Time tOFF_DLY SYMBOL IUVLO CONDITIONS UVLO = 2.460V MIN -1.5 50 7 TYP MAX +1.5 440 UNITS A mV s
MAX5942A/MAX5942B
VTH,G,UVLO (Note 8) UVLO = VEE
VIN, VUVLO falling (Note 9) TA = +25C Output current = 300mA, VGATE = 5.6V, (Note 11) measured between TA = +85C OUT and VEE OUT = GND, VGATE - VEE, output current < 1A Power-off mode, VIN = 12V, UVLO = VEE VGATE = 2V IGATE = 1A VOUT - VEE, |VOUT - VEE| decreasing, VGATE = 5.75V Hysteresis (GATE - VEE) increasing, OUT = VEE Hysteresis ISINK = 2mA (Note 10) ISINK = 2mA, OUT (GND - 5V) (Note 10) GATE = high, GND - VOUT = 67V (Note 10) GATE = VEE, PGOOD - VEE = 67V (Note 10)
0.32
ms
0.6 0.8 0.5 38 5 5.58 1.15 10 5.76 1.23 70 4.62 4.76 80
1.1 1.5 V 80 15 5.93 1.31 A V V mV 4.91 0.4 0.2 1 1 V mV V V A A
Isolation Switch N-Channel MOSFET On-Resistance
RON
Isolation Switch N-Channel MOSFET Off-Threshold Voltage GATE Pulldown Switch Resistance GATE Charging Current GATE High Voltage PGOOD, PGOOD Assertion VOUT Threshold PGOOD, PGOOD Assertion VGATE Threshold PGOOD Output Low Voltage PGOOD Output Low Voltage PGOOD Leakage Current PGOOD Leakage Current
VGSTH RG IG VGATE VOUTEN
VGSEN VOLDCDC
ELECTRICAL CHARACTERISTICS (PWM Controller)
(All voltages referenced to V-. VDD = 13V, a 10F capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1F capacitor connected to SS_SHDN, NDRV = open circuit, VFB = 3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SUPPLY CURRENT IV+(NS) V+ Supply Current V+ Supply Current After Startup IV+(S) VDD = 0V, V+ = 67V, driver not switching V+ = 67V, VDD = 0V, VFB = 4V, driver switching V+ = 67V, VDD = 13V, VFB = 4V 0.8 1.6 14 1.6 3.2 mA A SYMBOL CONDITIONS MIN TYP MAX UNITS
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
(All voltages referenced to V-. VDD = 13V, a 10F capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1F capacitor connected to SS_SHDN, NDRV = open circuit, VFB = 3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER VDD Supply Current V+ Shutdown Current VDD Shutdown Current PREREGULATORS/STARTUP V+ Input Voltage VDD Supply Voltage INTERNAL REGULATORS VCC Output Voltage VCC Undervoltage Lockout OUTPUT DRIVER Peak Source Current Peak Sink Current NDRV High-Side Driver Resistance NDRV Low-Side Driver Resistance ERROR AMPLIFIER FB Input Resistance FB Input Bias Current Error Amplifier Gain (Inverting) Closed-Loop 3dB Bandwidth FB Input Voltage Range SLOPE COMPENSATION Slope Compensation THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Hysteresis CURRENT LIMIT CS Threshold Voltage CS Input Bias Current Current-Limit Comparator Propagation Delay CS Blanking Time OSCILLATOR Clock Frequency Range Max Duty Cycle FB = VMAX5942A, FB = VMAX5942B, FB = V235 75 44 275 314 85 50 kHz % VILIM FB = 4V 0V VCS 2V, FB = 4V 25mV overdrive on CS, FB = VFB = GND, only PWM comparator is blanked 419 -1 180 70 465 510 +1 mV A ns ns +150 25 C C VSCOMP MAX5942A 26 mV/s 2 RIN IFB AVCL VFB = VSS_SHDN 50 1 -20 200 3 k A V/V kHz V ROH ROL VCC = 11V (externally forced) VCC = 11V (externally forced) VCC = 11V, externally forced, NDRV sourcing 50mA VCC = 11V, externally forced, NDRV sinking 50mA 570 1000 4 1.6 12 4 mA mA VCC_UVLO Powered from V+, ICC = 7.5mA, VDD = 0V Powered from VDD, ICC = 7.5mA VCC falling 7.5 9.0 9.8 10.0 6.6 12 11.0 V V 18 13 67 36 V V SYMBOL IVDD(NS) IVDD(S) CONDITIONS VDD = 36V, driver not switching VDD = 36V, driver switching, VOPTO = 4V VSS_SHDN = 0V, V+ = 67V VSS_SHDN = 0V MIN TYP 0.9 1.9 180 4 MAX 1.6 3.2 290 20 UNITS mA A A
4
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
(All voltages referenced to V-. VDD = 13V, a 10F capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1F capacitor connected to SS_SHDN, NDRV = open circuit, VFB = 3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SOFT-START SS Source Current SS Sink Current Peak Soft-Start Voltage Clamp Shutdown Threshold No external load VSS_SHDN falling (Note 11) VSS_SHDN rising (Note 11) ISSO VSS_SHDN = V2.0 1 2.331 0.25 0.53 2.420 0.37 0.59 2.500 0.41 0.65 4.5 6.5 A mA V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5942A/MAX5942B
All min/max limits for the PD interface are production tested at +85C (extended grade)/+70C (commercial grade). Limits at +25C and -40C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25C and +85C (extended grade)/+70C (commercial grade). Limits at -40C are guaranteed by design, unless otherwise noted. Note 2: The input offset current is illustrated in Figure 1. Note 3: Effective differential input resistance is defined as the differential resistance between GND and VEE without any external resistance. Note 4: Classification current is turned off whenever the IC is in power mode. Note 5: See Table 2 in the PD Classification Mode section. RDISC and RCL must be 100ppm or better. Note 6: See Thermal Dissipation section for details. Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k (1%), the turnon threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage. Note 8: When the VUVLO is below VTH, G, UVLO, the MAX5942_ sets the turn-on voltage threshold internally (VUVLO,ON). Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY will not cause the MAX5942A/MAX5942B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V). Note 10: PGOOD references to OUT while PGOOD references to VEE. Note 11: Guaranteed by design. Note 1:
IIN dRi 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) VINi dRi
IOFFSET IINi IINi +1 IINi
dRi
IOFFSET VINi 1V VINi +1
Figure 1. Effective Differential Input Resistance/Offset Current
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
Typical Operating Characteristics
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX. Typical values are at TA = +25C. All voltages are referenced to VEE (for graphs 1-11 in the Typical Operating Characteristics); all voltages are referenced to V- (for graphs 12-30 in the Typical Operating Characteristics), unless otherwise noted.
DETECTION CURRENT vs. INPUT VOLTAGE
MAX5942A/B toc01
CLASSIFICATION CURRENT vs. INPUT VOLTAGE
MAX5942A/B toc02
0.40 DETECTION CURRENT (mA) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0
RDISC = 25.5k GND = V+ = V- = OUT
35 CLASSIFICATION CURRENT (mA) 30 25 20 15 10
CLASS 4
3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10
CLASS 3
CLASS 2
CLASS 1 5 0 10 CLASS 0 15 20 INPUT VOLTAGE (V) 25 30
2
4
6
8
10
15
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OFFSET CURRENT vs. INPUT VOLTAGE
MAX5942A/B toc04
NORMALIZED UVLO vs. TEMPERATURE
MAX5942A/B toc05
PGOOD OUTPUT LOW VOLTAGE vs. CURRENT
180 160 140 VPGOOD (mV) 120 100 80 60 40 20 0
MAX5942A/B toc06
0 -0.5 OFFSET CURRENT (A) -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 1 2 3 4 5 6 7 8 9
1.010 1.008 1.006 NORMALIZED UVLO 1.004 1.002 1.000 0.998 0.996 0.994 0.992 0.990 UVLO = VEE
200
10 11
-40
-15
10
35
60
85
0
4
8
12
16
20
INPUT VOLTAGE (V)
TEMPERATURE (C)
ISINK (mA)
PGOOD OUTPUT LOW VOLTAGE vs. CURRENT
MAX5942A/B toc07
OUT LEAKAGE CURRENT vs. TEMPERATURE
VOUT = 67V OUT LEAKAGE CURRENT (nA) 16
MAX5942A/B toc08
INRUSH CURRENT CONTROL (VIN = 12V)
400 350 300 VPGOOD (mV) 250 200 150 100 50 0 0 4 8 12 16
MAX5942A/B toc09
20
MAX5942A/B toc03
0.45
40
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (M)
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE vs. INPUT VOLTAGE
3.5
VGATE 5V/div
12
IINRUSH 100mA/div VOUT 10V/div
8
4 PGOOD 10V/div -40 -15 10 35 60 85 1ms/div
0 20 ISINK (mA) INPUT VOLTAGE (V)
6
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX. Typical values are at TA = +25C. All voltages are referenced to VEE (for graphs 1-11 in the Typical Operating Characteristics); all voltages are referenced to V- (for graphs 12-30 in the Typical Operating Characteristics), unless otherwise noted.
INRUSH CURRENT CONTROL (VIN = 48V) INRUSH CURRENT CONTROL (VIN = 67V)
MAX5942A/B toc11
MAX5942A/MAX5942B
VSS_SHDN vs. TEMPERATURE (AT THE END OF SOFT-START)
VSS_SHDN (V) (NORMALIZED TO VREF = 2.4V) VFB = V1.002
MAX5942 toc12
MAX5942A/B toc10
1.003
VGATE 5V/div
VGATE 5V/div IINRUSH 100mA/div
IINRUSH 100mA/div
1.001
VOUT 50V/div
VOUT 50V/div PGOOD 50V/div 2ms/div
1.000
PGOOD 50V/div 2ms/div
0.999 -40 -20 0 20 40 60 80 TEMPERATURE (C)
NDRV FREQUENCY vs. TEMPERATURE
MAX5942 toc13
MAX5942A MAXIMUM DUTY CYCLE vs. TEMPERATURE
MAX5942 toc14
MAX5942B MAXIMUM DUTY CYCLE vs. TEMPERATURE
MAX5942 toc15
278
81.0 80.9 80.8 80.7 80.6 80.5 80.4 FB = V-
48.0 47.8 FB = V47.6 47.4 47.2 47.0 46.8
MAXIMUM DUTY CYCLE (%)
FB = V276
275
274
273 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-40
-20
0
20
40
60
80
MAXIMUM DUTY CYCLE (%)
277 NDRV FREQUENCY (kHz)
-40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
V+ SUPPLY CURRENT vs. TEMPERATURE
MAX5942 toc16
SOFT-START SOURCE CURRENT vs. TEMPERATURE
SOFT-START SOURCE CURRENT (A) 4.49 4.48 4.47 4.46 4.45 4.44 4.43 4.42 4.41 4.40 13.50 -40 -20 0 20 40 60 80 -40
MAX5942 toc17
V+ INPUT CURRENT vs. TEMPERATURE (AFTER STARTUP)
MAX5942 toc18
1.64 1.63 V+ SUPPLY CURRENT (mA) 1.62 1.61 1.60 1.59 1.58 1.57 1.56 1.55 -40 -20 40 TEMPERATURE (C) 0 20 60 80 FB = VDD = V-
4.50 VDD = FB = SS_SHDN = VV+ = 67V
13.80 13.75 V+ INPUT CURRENT (A) V+ = 67V, VDD = 13V, FB = V13.70 13.65 13.60 13.55
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX. Typical values are at TA = +25C. All voltages are referenced to VEE (for graphs 1-11 in the Typical Operating Characteristics); all voltages are referenced to V- (for graphs 12-30 in the Typical Operating Characteristics), unless otherwise noted.
V+ SHUTDOWN CURRENT vs. TEMPERATURE
MAX5942 toc19
CS THRESHOLD VOLTAGE vs. TEMPERATURE
MAX5942 toc20
182.5 V+ SHUTDOWN CURRENT (A) 182.0 V+ = 67V, FB = SS_SHDN = V181.5 181.0 180.5 180.0 179.5 179.0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0.488
CS THRESHOLD VOLTAGE (V)
0.487 FB = V0.486
0.485
0.484
0.483 -40 -20 0 20 40 60 80 TEMPERATURE (C)
NDRV RESISTANCE vs. TEMPERATURE
MAX5942 toc21
CURRENT-LIMIT DELAY vs. TEMPERATURE
208 CURRENT-LIMIT DELAY (ns) 206 204 202 200 198 196 194 192 190 188 FB = V-, 100mV OVERDRIVE ON CS
MAX5942 toc22
5.0 4.5 NDRV RESISTANCE () 4.0 HIGH-SIDE DRIVER 3.5 3.0 2.5 2.0 1.5 1.0 -40 -20 40 TEMPERATURE (C) 0 20 60 80 LOW-SIDE DRIVER
210
-40
-20
0
20
40
60
80
TEMPERATURE (C)
VSS_SHDN vs. VDD
MAX5942 toc23
NDRV FREQUENCY vs. VDD
270.5 NDRV FREQUENCY (kHz) 270.0 269.5 269.0 268.5 FB = V268.0 267.5
MAX5942 toc24
2.410
271.0
2.408 VSS_SHDN (V)
2.406
2.404
2.402
2.400 0 5 10 15 20 VDD (V) 25 30 35 40
267.0 0 5 10 15 20 VDD (V) 25 30 35 40
8
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX. Typical values are at TA = +25C. All voltages are referenced to VEE (for graphs 1-11 in the Typical Operating Characteristics); all voltages are referenced to V- (for graphs 12-30 in the Typical Operating Characteristics), unless otherwise noted.
MAX5942B MAXIMUM DUTY CYCLE vs. VDD
MAX5942 toc25
MAX5942A/MAX5942B
47.9 MAXIMUM DUTY CYCLE (%) 47.8 47.7 47.6 47.5 47.4 47.3 47.2 47.1 47.0 0 5 10 15 20 VDD (V) 25 30 35 DEVICE POWERED FROM V+ VFB = 4V, CS = V-
10.1 10.0 VCC (V) 9.9
DEVICE POWERED FROM VDD
DEVICE POWERED FROM VDD
FB = V9.8 9.7 9.6 DEVICE POWERED FROM V+ 0 5 10 15 20 VDD (V) 25 30 35 40
40
9.5
V+ SUPPLY CURRENT vs. V+ VOLTAGE
MAX5942 toc27
V+ SUPPLY CURRENT vs. V+ VOLTAGE (AFTER STARTUP)
14 V+ LEAKAGE CURRENT (A) 12 10 8 6 4 2 0 VDD = 13V, FB = VMAX5942 toc28
1.60 1.59 V+ SUPPLY CURRENT (mA) 1.58 1.57 1.56 1.55 1.54 1.53 1.52 1.51 0 20 40 60 80 100 V+ VOLTAGE (V) VFB = VDD = V-
16
0 10 20 30 40 50 60 70 80 90 100 110 V+ VOLTAGE (V)
VCC VOLTAGE vs. VCC CURRENT
MAX5942 toc29
VCC VOLTAGE vs. VCC CURRENT
9.9 9.8 VCC VOLTAGE (V) 9.7 9.6 9.5 9.4 9.3 9.2 V+ = 36V V+ = 24V V+ = 67V V+ = 48V VDD = GND, VFB = 4V
MAX5942 toc30
10.4 V+ = +67V, VFB = 4V 10.2 VDD = 36V VCC VOLTAGE (V) 10.0 9.8 VDD = 13V 9.6 9.4 9.2 9.0 0 5 10 15 VCC CURRENT (mA)
10.0
9.1 9.0 20 0 5 10 VCC CURRENT (mA) 15 20
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MAX5942 toc26
48.0
VCC vs. VDD
10.2
9
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
Pin Description
PIN 1 NAME V+ FUNCTION High-Voltage Startup Input. Referenced to V-. Connect directly to an input voltage range between 18V to 67V. Connects internally to a high-voltage linear regulator that generates VCC during startup. Line Regulator Input. Referenced to V-. VDD is the input to the linear regulator that generates VCC. For supply voltages less than 36V, connect VDD and V+ to the supply. For supply voltages greater than 36V, VDD receives its power from the tertiary winding of the transformer and accepts voltages from 13V to 36V. Bypass VDD to V- with a 4.7F capacitor. Fixed-Gain Inverting Amplifier Input. Referenced to V-. Connect a voltage-divider from the regulated output to FB. The noninverting input of the amplifier is referenced to +2.4V
2
VDD
3
FB
4
Soft-Start Timing Capacitor Connection. Referenced to V-. Ramp time to full current limit is approximately SS_SHDN 0.45ms/nF. Bypass with a minimum 10nF capacitor to V-. A 2.4V reference voltage appears across the capacitor. Disable the PWM controller by pulling SS_SHDN below 0.25V. Undervoltage Lockout Programming Input for Power Mode. Referenced to VEE. When UVLO is above its threshold, the device enters the power mode. Connect UVLO to VEE to use the default undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series resistance value of the external resistors must add to 25.5k (1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull UVLO between VTH,G,UVLO and VREF,UVLO. Classification Setting. Referenced to VEE. Add a resistor from RCL to VEE to set a PD class (see Table 1). Gate of Internal N-Channel Power MOSFET. Referenced to VEE . GATE sources 10A when the device enters the power mode. Connect an external 100V ceramic capacitor from GATE to VOUT to program the inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection and classification functions operate normally when GATE is pulled to VEE. N e ga t ive I n p u t P o w e r . S o u r ce o f th e in te g r a t ed iso la t io n N - c h a nn e l p ow e r MOS F E T . C o n n e ct V EE t o - 4 8V . Output Voltage. Referenced to VEE. Drain of the integrated isolation N-channel power MOSFET. Connect OUT to V-. Power-Good Indicator Output, Active High, Open Drain. PGOOD is referenced to OUT. PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled to OUT (given that VOUT is at least 5V below GND). Power-Good Indicator Output, Active Low, Open Drain. PGOOD is referenced to VEE. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high impedance. Ground. Referenced to VEE. GND is the positive input power. Current-Sense Input. Referenced to V-. Turns power switch off if VCS rises above 465mV for cycle-by-cycle current limiting. CS is also the feedback for the current-mode controller. CS connects to the PWM controller through a leading-edge blanking circuit. Ground. V- is the ground terminal of the PWM controller. Gate Drive. Referenced to V-. Drives a high-voltage external N-channel power MOSFET. Regulated IC Supply. Referenced to V-. Provides power for MAX5942_. VCC is regulated from VDD during normal operation and from V+ during startup. Bypass VCC with a 10F tantalum capacitor in parallel with a 0.1F ceramic capacitor to V-.
5
UVLO
6
RCL
7
GATE
8 9
VEE OUT
10
PGOOD
11 12 13 14 15 16
PGOOD GND CS VNDRV VCC
10
______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B MAX5942A/MAX5942B
Table 1. PD Power Classification/RCL Selection
CLASS 0 1 2 3 4 USAGE Default Optional Optional Optional Not allowed RCL () 10k 732 392 255 178 MAXIMUM POWER USED BY PD (W) 0.44 to 12.95 0.44 to 3.84 3.84 to 6.49 6.49 to 12.95 Reserved*
*Class 4 reserved for future use.
Detailed Description
The MAX5942A/MAX5942B integrate a complete power IC for powered devices (PD) in a power-over-ethernet (PoE) system. The MAX5942A/MAX5942B provide PD Interface and a compact DC-DC PWM controller suitable for flyback and forward converters in either isolated or nonisolated designs. The MAX5942A/MAX5942B PD interface complies with the IEEE 802.3af standard, providing the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. These devices also feature power-mode undervoltage lockout (UVLO) with wide hysteresis, and power-good status outputs. An integrated MOSFET provides PD isolation during detection and classification. The MAX5942A/MAX5942B guarantee a leakage current offset of less than 10A during the detection phase. A programmable current limit prevents high inrush current during power-on. The devices feature power-mode UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to ensure glitch-free transition between detection, classification, and power-on/off phases. The MAX5942A/MAX5942B provide both activehigh (PGOOD) and active-low (PGOOD) outputs. Both devices offer an adjustable UVLO threshold with a default value compliant to the IEEE 802.3af standard. The MAX5942A/MAX5942B are designed to work with or without an external diode bridge in front of the PD. Use the MAX5942A/MAX5942B PWM current-mode controllers to design flyback- or forward-mode power supplies. Current-mode operation simplifies control-loop design while enhancing loop stability. An internal highvoltage startup regulator allows the device to connect directly to the input supply without an external startup resistor. Current from the internal regulator starts the controller. Once the tertiary winding voltage is established, the internal regulator is switched off and bias current for running the PWM controller is derived from the tertiary winding. The internal oscillator is set to 275kHz and trimmed to 10%. This permits the use of small
magnetic components to minimize board space. Both the MAX5942A and MAX5942B can be used in power supplies providing multiple output voltages. A functional diagram of the PWM controller is shown in Figure 4. Typical application circuits for forward and flyback topologies are shown in Figure 5 and Figure 6, respectively.
Powered Device Interface
Operating Modes The PD front-end section of the MAX5942A/MAX5942B operates in three different modes: PD detection signature, PD classification, and PD power, depending on its input voltage (VIN = GND - VEE). All voltage thresholds are designed to operate with or without the optional diode bridge while still complying with the IEEE 802.3af standard (see Application Circuit 1). Detection Mode (1.4V VIN 10.1V) In detection mode, the power source equipment (PSE) applies two voltages on VIN in the range of 1.4V to 10.1V (1V step minimum), and then records the current measurements at the two points. The PSE then computes V/I to ensure the presence of the 25.5k signature resistor. In this mode, most of the MAX5942A/MAX5942B internal circuitry is off and the offset current is less than 10A. If the voltage applied to the PD is reversed, install protection diodes on the input terminal to prevent internal damage to the MAX5942A/MAX5942B (see Figures 8 and 9). Since the PSE uses a slope technique (V/I) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process. Classification Mode (12.6V VIN 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. The IEEE 802.3af standard defines five different classes as shown in Table 1. An external resistor (RCL) connected from RCL to VEE sets the classification current.
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11
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
Table 2. Setting Classification Current
CLASS 0 1 2 3 4 RCL () 10k 732 392 255 178 VIN* (V) 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 CLASS CURRENT SEEN AT VIN (mA) MIN 0 9 17 26 36 MAX 4 12 20 30 42 IEEE 802.3af PD CLASSIFICATION CURRENT SPECIFICATION (mA) MIN 0 9 17 26 36 MAX 4 12 20 30 44
*VIN is measured across the MAX5942 input pins (VEE and GND), which does not include the diode bridge voltage drop.
GND UVLO GND R1 21.8V 2.4V, 0.8 HYST PGOOD REF 2.4V, REF EN 6.8V
CLASSIFICATION
RCL
MAX5942B
Q4
R2 39V
R3 VGATE, 6V EN 1.2V, REF PGOOD 5V, REF Q3
UVLO
200mV GATE
Q2 Q1
VOUT
VEE
Figure 2. Powered Device Interface Block Diagram
12
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IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
The PSE determines the class of a PD by applying a voltage at the PD input and measures the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the MAX5942A/MAX5942B exhibit a current characteristic with values indicated in Table 2. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by the 25.5k detection signature resistor and the supply current of the MAX5942A/MAX5942B so that the total current drawn by the PD is within the IEEE 802.3af standard figures. The classification current is turned off whenever the device is in power mode. Power Mode During power mode, when VIN rises above the undervoltage lockout threshold (V UVLO,ON ), the MAX5942A/ MAX5942B gradually turn on the internal N-channel MOSFET Q1 (see Figure 2). The MAX5942A/MAX5942B charge the gate of Q1 with a constant current source (10A, typ). The drain-to-gate capacitance of Q1 limits the voltage rise rate at the drain of MOSFET, thereby limiting the inrush current. To reduce the inrush current, add external drain-to-gate capacitance (see the Inrush Current section). When the drain of Q1 is within 1.2V of its source voltage and its gate-to-source voltage is above 5V, the MAX5942A/MAX5942B assert the PGOOD/ PGOOD outputs. The MAX5942A/MAX5942B have a wide UVLO hysteresis and turn-off deglitch time to compensate for the high impedance of the twisted-pair cable.
MAX5942A/MAX5942B MAX5942A/MAX5942B
VIN = 24V TO 60V
GND R1
UVLO
MAX5942A MAX5942B
R2 VEE
Figure 3. Setting Undervoltage Lockout with an External Resistor-Divider
1%. When using the external resistor-divider, the MAX5942 has an external reference voltage hysteresis of 20% (typ). In other words, when UVLO is programmed externally, the turn-off threshold will be 80% (typ) of the new UVLO turn-on threshold.
Inrush Current Limit
The MAX5942A/MAX5942B charge the gate of the internal MOSFET with a constant current source (10A, typ). The drain-to-gate capacitance of the MOSFET limits the voltage rise rate at the drain, thereby limiting the inrush current. Add an external capacitor from GATE to OUT to further reduce the inrush current. Use the following equation to calculate the inrush current: IINRUSH = IG x COUT CGATE
Undervoltage Lockout
The MAX5942A/MAX5942B operate up to a 67V supply voltage with a default UVLO turn-on set at 39V and a UVLO turn-off set at 30V. Adjust the UVLO threshold using a resistor-divider connected to UVLO (see Figure 3). When the input voltage is above the UVLO threshold (VUVLO,ON), the IC is in power mode and the MOSFET is on. When the input voltage goes below the UVLO threshold (VUVLO,OFF) for more than tOFF_DLY, the MOSFET turns off. To adjust the UVLO threshold, connect an external resistor-divider from GND to UVLO and from UVLO to VEE. Use the following equations to calculate R1 and R2 for a desired UVLO threshold: R2 = 25.5k x VREF, UVLO VINEX ,
The recommended inrush current for a PoE application is 100mA.
PGOOD/PGOOD Outputs
PGOOD is an open-drain, active-high logic output. PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled to VOUT (given that VOUT is at least 5V below GND). Connect PGOOD to SS_SHDN to enable the PWM controller. PGOOD is an open-drain, active-low logic output. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high impedance.
R1 = 25.5k - R2 where VIN,EX is the desired UVLO threshold. Since the resistor-divider replaces the 25.5k PD detection resistor, ensure that the sum of R1 and R2 equals 25.5k
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13
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
Thermal Dissipation
During classification mode, if the PSE applies the maximum DC voltage, the maximum voltage drop from GND to VRCL will be 13V. If the maximum classification current of 42mA flows through the MAX5942A/ MAX5942B, then the maximum DC power dissipation will be close to 546mW, which is slightly higher than the maximum DC power dissipation the IC can handle. However, according to the IEEE 802.3af standard, the duration of the classification mode is limited to 75ms (max). The MAX5942A/MAX5942B handle the maximum classification power dissipation for the maximum duration time without sustaining any internal damage. If the PSE violates the IEEE 802.3af standard by exceeding the 75ms maximum classification duration, it may cause internal damage to the IC.
Internal Regulators
The internal regulators of the MAX5942A/MAX5942B enable initial startup without a lossy startup resistor and regulate the voltage at the output of a tertiary (bias) winding to provide power for the IC. At startup, V+ is regulated down to VCC to provide bias for the device. The VDD regulator then regulates from the output of the tertiary winding to VCC. This architecture allows the tertiary winding to have only a small filter capacitor at its output, thus eliminating the additional cost of a filter inductor. When designing the tertiary winding, calculate the number of turns so the minimum reflected voltage is always higher than 12.7V. The maximum reflected voltage must be less than 36V. To reduce power dissipation, the high-voltage regulator is disabled when the VDD voltage reaches 12.7V. This greatly reduces power dissipation and improves efficiency. If V CC falls below the undervoltage lockout threshold (VCC = 6.6V), the low-voltage regulator is disabled, and soft-start is reinitiated. In undervoltage lockout, the MOSFET driver output (NDRV) is held low. If the input voltage range is between 13V and 36V, V+ and VDD may be connected to the line voltage, provided that the maximum power dissipation is not exceeded. This eliminates the need for a tertiary winding.
PWM Controller
Current-Mode Control The MAX5942A/MAX5942B offer current-mode control operation with added features such as leading-edge blanking with dual internal path that only blanks the sensed current signal applied to the input of the PWM comparator. The current-limit comparator monitors the CS pin at all times and provides cycle-by-cycle current limit without being blanked. The leading-edge blanking of the CS signal prevents the PWM comparator from prematurely terminating the on cycle. The CS signal contains a leading-edge spike that is the result of the MOSFET gate charge current, capacitive and diode reverse recovery current of the power circuit. Since this leading-edge spike is normally lower than the currentlimit comparator threshold, current limiting is not blanked and cycle-by-cycle current limiting is provided under all conditions. Use the MAX5942A in discontinuous flyback applications where wide line voltage and load current variation are expected. Use the MAX5942B for single-transistor forward converters where the maximum duty cycle must be limited to less than 50%. Under certain conditions, it may be advantageous to use a forward converter with greater than 50% duty cycle. For those cases, use the MAX5942A. The large duty cycle results in much lower operating primary RMS currents through the MOSFET switch and in most cases a smaller output filter inductor. The major disadvantage to this is that the MOSFET voltage rating must be higher and that slope compensation must be provided to stabilize the inner current loop. The MAX5942A provides internal slope compensation.
PWM Controller Undervoltage Lockout, Soft-Start, and Shutdown
The soft-start feature of the MAX5942A/MAX5942B allows the load voltage to ramp up in a controlled manner, thus eliminating output voltage overshoot. While the part is in undervoltage lockout, the capacitor connected to the SS_SHDN pin is discharged. Upon coming out of undervoltage lockout, an internal current source starts charging the capacitor to initiate the softstart cycle. Use the following equation to calculate total soft-start time: tstartup = 0.45 ms x Css nF
where CSS is the soft-start capacitor as shown in Figure 5. Operation begins when VSS_SHDN ramps above 0.6V. When soft-start has completed, VSS_SHDN is regulated to 2.4V, the internal voltage reference. Pull VSS_SHDN below 0.25V to disable the controller. Undervoltage lockout shuts down the controller when VCC is less than 6.6V. The regulators for V+ and the reference remain on during shutdown.
14
______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
VDD VDD-OK V+ IN HIGHVOLTAGE REGULATOR EN OUT EN BIAS WINDING REGULATOR OUT 0.7V VCC IN
V-
MAX5942A ONLY SLOPE COMPENSATION 26mV/s 26mV/s 6.6V
UVLO 275kHz OSCILLATOR VCC R NDRV Q 80%/50% DUTY CYCLE CLAMP PWM ILIM 125mV CS S
1M 50k
FB
ERROR AMP
5k VCC SS_SHDN 4A 70ns BLANKING
2.4V BUF
3R
R
0.25V
Figure 4. MAX5942A/MAX5942B PWM Controller Functional Diagram ______________________________________________________________________________________ 15
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
1N4148 VIN (36V TO 72V) 6 NT N 14 R CMHD2003 CIN 3 0.47F NP 14 M1 IRF640N SBL204OCT L1 4.7H VOUT 5V/10A COUT 3 560F 0.1F
VDD CDD 4.7F
GND
V+
NS 5
20 1nF
RCL VCC 25.5k RCL CCC 10F
NDRV
MAX5942
CS 100 RSENSE 100m
R1 2k
VUVLO SS_SHDN CSS 0.1F PGOOD GATE VEE GATE FB CFB (OPTIONAL) R2 2k OUT
Figure 5. Forward Converter
Current-Sense Comparator
The current-sense (CS) comparator and its associated logic limit the peak current through the MOSFET. Current is sensed at CS as a voltage across a sense resistor between the source of the MOSFET and GND. To reduce switching noise, connect CS to the external MOSFET source through a 100 resistor or an RC lowpass filter (Figures 5, 6). Select the current-sense resistor, RSENSE according to the following equation: RSENSE = 0.465V / ILIMPrimary where ILIMPrimary is the maximum peak primary-side current. When VCS > 465mV, the power MOSFET switches off. The propagation delay from the time the switch current reaches the trip level to the driver turn-off time is 180ns.
Figure 5). Calculate the output voltage using the following equation: R VOUT = 1+ 1 x VREF R2 where VREF = 2.4V. Choose R1//R2 << RIN, where RIN 50k is the input resistance of FB. The gain of the error amplifier is internally configured for -20 (see Figure 4). The error amplifier may also be used to regulate the output of the tertiary winding for implementing a primaryside regulated isolated power supply (see Figure 7). Calculate the output voltage using the following equation: VOUT = NS R1 1+ x VREF NT R2
Internal Error Amplifier
The MAX5942A/MAX5942B include an internal error amplifier that can be used to regulate the output voltage in the case of a nonisolated power supply (see
where NS is the number of secondary turns and NT is the number of tertiary winding turns.
16
______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
NT VIN GND V+ CIN NP NS COUT VOUT
VDD CDD
RCL VCC 25.5k RCL CCC
NDRV CS
M1
MAX5942
100
RSENSE
R1
PGOOD SS_SHDN CSS PGOOD UVLO VEE GATE
V-
OUT
FB R2
Figure 6. Flyback Converter
VIN VDD CDD R1 FB R2 25.5k CCC PGOOD VCC NDRV CS GND V+
NT COUT NP NS
VOUT CIN
M1
MAX5942
100 GATE RSENSE
RCL SS_SHDN CSS RCL PGOOD UVLO
VOUT
VEE
Figure 7. Flyback Converter ______________________________________________________________________________________ 17
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
PWM Comparator and Slope Compensation
An internal 275kHz oscillator determines the switching frequency of the controller. At the beginning of each cycle, NDRV switches the N-channel MOSFET on. NDRV switches the external MOSFET off after the maximum duty cycle has been reached, regardless of the feedback. The MAX5942B uses an internal ramp generator for slope compensation. The internal ramp signal is reset at the beginning of each cycle and slews at 26mV/s. The PWM comparator uses the instantaneous current, the error voltage, the internal reference, and the slope compensation (MAX5942A only) to determine when to switch the N-channel MOSFET off. In normal operation, the N-channel MOSFET turns off when: IPRIMARY x RSENSE > VEA - VREF - VSCOMP where IPRIMARY is the current through the N-channel MOSFET, VREF is the 2.4V internal reference, VEA is the output voltage of the internal amplifier, and VSCOMP is a ramp function starting at zero and slewing at 26mV/s (MAX5942A only). When using the MAX5942A in a forward-converter configuration, the following condition must be met to avoid control-loop subharmonic oscillations: NS k x RSENSE x VOUT x = 26mV/s L NP where k = 0.75 to 1, and NS and NP are the number of turns on the secondary and primary side of the transformer, respectively. L is the output filter inductor. This makes the output inductor current downslope as referenced across RSENSE equal to the slope compensation. The controller responds to transients within one cycle when this condition is met.
Applications Information
Design Example
The following is a general procedure for designing a forward converter using the MAX5942B: 1) Determine the requirements. 2) Set the output voltage. 3) Calculate the transformer primary to secondary winding turns ratio. 4) Calculate the reset to primary winding turns ratio. 5) Calculate the tertiary to primary winding turns ratio. 6) Calculate the current-sense resistor value. 7) Calculate the output inductor value. 8) Select the output capacitor. The circuit in Figure 5 was designed as follows: 1) 30V VIN 67V, VOUT = 5V, IOUT = 10A, VRIPPLE 50mV. Turn-on threshold is set at 38.6V. 2) To set the output voltage, calculate the values of resistors R1 and R2 according to the following equation:
R1 VOUT = VREF 1 + R2 R1// R2 << 50k VREF = VSS _ SHDN = 2.4V
where VREF is the reference voltage of the shunt regulator, and R1 and R2 are the resistors shown in Figures 5 and 6. 3) The turns ratio of the transformer is calculated based on the minimum input voltage and the lower limit of the maximum duty cycle for the MAX5942B (44%). To enable the use of MOSFETs with drain-source breakdown voltages of less than 200V, use the MAX5942B with the 50% maximum duty cycle. Calculate the turns ratio according to the following equation: NS VOUT + (VD1 x DMAX ) NP DMAX x VIN_MIN where: NS/NP = Turns ratio (NS is the number of secondary turns and NP is the number of primary turns).
N-Channel MOSFET Gate Driver
NDRV drives an N-channel MOSFET. NDRV sources and sinks large transient currents to charge and discharge the MOSFET gate. To support such switching transients, bypass VCC with a ceramic capacitor. The average current as a result of switching the MOSFET is the product of the total gate charge and the operating frequency. It is this current plus the DC quiescent current that determines the total operating current.
18
______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
VOUT = Output voltage (5V). VD1 = Voltage drop across D1 (typically 0.5V for power Schottky diodes). DMAX = Minimum value of maximum operating duty cycle (44%). VIN_MIN = Minimum input voltage (30V). In this example: NS 5V + (0.5V x 0.44) = 0.395 0.44 x 30V NP Choose N P based on core losses and DC resistance. Use the turns ratio to calculate NS, rounding up to the nearest integer. In this example, NP = 14 and NS = 6. For a forward converter, choose a transformer with a magnetizing inductance in the neighborhood of 200H. Energy stored in the magnetizing inductance of a forward converter is not delivered to the load and must be returned back to the input; this is accomplished with the reset winding. The transformer primary to secondary leakage inductance should be less than 1H. Note that all leakage energy is dissipated across the MOSFET. Snubber circuits may be used to direct some or all of the leakage energy to be dissipated across a resistor. To calculate the minimum duty cycle (DMIN), use the following equation: VOUT = DMIN = NS VIN_MAX x - VD1 NP where VIN_MAX is the maximum input voltage (67V). 4) The reset winding turns ratio (NR/NP) needs to be low enough to guarantee that the entire energy in the transformer is returned to V+ within the off cycle at the maximum duty cycle. Use the following equation to determine the reset winding turns ratio: NR NP x 1-DMAX DMAX
MAX5942A/MAX5942B
NR 14 x
1- 0.5 = 14 0.5
Round NR to the nearest smallest integer. The turns ratio of the reset winding (NR/NP) determines the peak voltage across the N-channel MOSFET. Use the following equation to determine the maximum drain-source voltage across the N-channel MOSFET: N VDSMAX VIN_MAX x 1 + P NR VDSMAX = Maximum MOSFET drain-source voltage. VIN_MAX = Maximum input voltage: 14 VDSMAX 67V x 1 + = 134V 14 Choose MOSFETs with appropriate avalanche power ratings to absorb any leakage energy. 5) Choose the tertiary winding turns ratio (NT/NP) so that the minimum input voltage provides the minimum operating voltage at VDD (13V). Use the following equation to calculate the tertiary winding turns ratio: VDDMIN + 0.7 x NP NT VIN_MIN VDDMAX + 0.7 x NP VIN_MAX where: VDDMIN is the minimum VDD supply voltage (13V). VDDMAX is the maximum VDD supply voltage (30V). VIN_MIN is the minimum input supply voltage (30V). VIN_MAX is the maximum input supply voltage (67V in this design example). NP is the number of turns of the primary winding. NT is the number of turns of the tertiary winding: 13.7 36.7 x 14 NT x 14 30 67 6.39 NT 7.67 Choose NT = 7.
where: NR/NP = Reset winding turns ratio. DMAX' = Maximum value of maximum duty cycle:
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19
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
Table 3. Component Suppliers
COMPONENT Power FETS Fairchild Vishay-Siliconix Current-Sense Resistors Dale-Vishay IRC ON Semi Diodes General Semiconductor Central Semiconductor Sanyo Capacitors Taiyo Yuden AVX Coiltronics Magnetics Coilcraft Pulse Engineering SUPPLIERS International Rectifier www.irf.com www.fairchildsemi.com www.vishay.com/brands/siliconix/main.html www.vishay.com/brands/dale/main.html www.irctt.com/pages/index.cfm www.onsemi.com www.gensemi.com www.centralsemi.com www.sanyo.com www.t-yuden.com www.avxcorp.com www.cooperet.com www.coilcraft.com www.pulseeng.com WEBSITE
6) Choose RSENSE according to the following equation: RSENSE VILIM NS x 1.2 x IOUTMAX NP
8) The size and ESR of the output filter capacitor determine the output ripple. Choose a capacitor with a low ESR to yield the required ripple voltage. Use the following equations to calculate the peak-topeak output ripple:
2 2 VRIPPLE = VRIPPLE,ESR + VRIPPLE,C
where: VILIM is the current-sense comparator trip threshold voltage (0.465V). NS/NP is the secondary-side turns ratio (5/14 in this example). IOUTMAX is the maximum DC output current (10A in this example): RSENSE 0.465V = 90.4m 6 x 1.2 x 10 14
where: VRIPPLE is the combined RMS output ripple due to VRIPPLE,ESR, the ESR ripple, and V RIPPLE,C , the capacitive ripple. Calculate the ESR ripple and capacitive ripple as follows: VRIPPLE,ESR = IRIPPLE x ESR VRIPPLE,C = IRIPPLE/(2 x x 275kHz x COUT)
Layout Recommendations
All connections carrying pulsed currents must be very short, be as wide as possible, and have a ground plane as a return path. The inductance of these connections must be kept to a minimum due to the high di/dt of the currents in high-frequency switching power converters. Current loops must be analyzed in any layout proposed, and the internal area kept to a minimum to reduce radiated EMI. Ground planes must be kept as intact as possible.
7) Choose the inductor value so that the peak ripple current (LIR) in the inductor is between 10% and 20% of the maximum output current: L
2 x LIR x 275kHz x IOUTMAX
(VOUT + VD ) x (1- DMIN )
where VD is the output Schottky diode forward-voltage drop (0.5V) and LIR is the ratio of inductor ripple current to DC output current: L
20
0.4 x 275kHz x 10A
(5.5) x (1- 0.198)
= 4.01H
______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
POWER-OVER SIGNAL PAIRS 3 6 1 2 RX PHY GND
+
VREG
DF025A
+ -
DF025A
RJ-45
-
4 5 7 8
TX -48V
POWER-OVER SPARE PAIRS
VREG
V+ VDD
GND
NDRV CS
MAX5942
*D1 GND **R1 SMBJ58CA RDISC = 25.5k 68nF **R2 GATE *D2 -48V FB UVLO RCL PGOOD PGOOD VCC VSS_SHDN
60V
VEE
OUT
CGATE* * OPTIONAL. ** R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL TO 25.5k AND REPLACE THE 25.5k RESISTOR.
Figure 8. PD with Power-Over-Ethernet (Power is Provided by Either the Signal Pairs or the Spare Pairs) ______________________________________________________________________________________ 21
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
POWER-SUPPLY CIRCUIT 1 VREG1
V+ VDD
GND
NDRV CS
MAX5942
*D1 GND **R1 RDISC = 25.5k 60V 68nF **R2 RCL *D2 -48V GATE FB UVLO RCL PGOOD PGOOD VCC VSS_SHDN
VEE
OUT
POWER-SUPPLY CIRCUIT 2
CGATE*
V+ VREG2
V+ VDD
NDRV CS
MAX5019
VCC GND
SS_SHDN FB
*OPTIONAL. **R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL TO 25.5k AND REPLACE THE 25.5k RESISTOR.
Figure 9. Power-Supply Circuit 1 Enabling PWM Controller of a Second Power Circuit 22 ______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
Typical Operating Circuit
MAX5942A/MAX5942B
VREG
V+ VDD
GND
NDRV CS
MAX5942
VCC GND UVLO RDISC = 25.5k 60V GATE FB RCL VSS_SHDN PGOOD PGOOD
-48V
VEE
OUT
CGATE
Chip Information
TRANSISTOR COUNT: 4232 PROCESS: BiCMOS
______________________________________________________________________________________
23
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices MAX5942A/MAX5942B
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
28L 16L SOIC.EPS
MAX5942A/MAX5942B
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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